It has been shown in recent years that semiconducting thin conductor filaments, so-called nanowires, made of a material from a multiplicity of material classes, such as e.g. Si, Ge, GaAs, GaN, CdS, CdTe, ZnO, etc., can be grown by solid-state reactions. By way of example, with the aid of silicide-forming metals with silicon-containing gases, it is possible to grow thin silicon nanowires having diameters of approximately 1 nm to 400 nm at temperatures of typically 400° C. These silicon nanowires may be doped in n-conducting fashion and p-conducting fashion and may also be modulation-doped. Moreover, they may be oxidized in sections. Owing to the possibility of forming PN junctions in a nanowire, it is thus possible to produce diodes or transistors which may be arranged in particular vertically with respect to the circuit planes of an IC chip. The nanowires may also be used as a vertical electrically conductive connection between wiring planes. Oxidized regions within the nanowire may be provided as an interruption. The production of such nanowires is described e.g. in US 2003/0089899 A1 and in the publication by Y. Cui et al. in Applied Physics Letters 78, 2214-2216 (2001).
Thin contact holes having a typical diameter of the nanowires to be produced of 1 nm to 400 nm are produced in a dielectric layer, in particular an intermetal dielectric between wiring planes of a chip, (e.g. made of silicon dioxide. Gold is deposited onto the bottom of the contact holes with a thickness of approximately 0.2 nm to 20 nm. Optionally, it is also possible to deposit gold clusters of suitable size (e.g. Au-30 cluster to Au-3000 cluster) at the bottom of the holes. Under a suitable silicon-containing atmosphere e.g. with silane, silicon is introduced into the gold. The silicon is separated from the gold and grown in the form of a thin silicon filament within the contact hole, the deposited gold being raised and as it were floating on the surface of the nanowire. In this way, the entire contact hole can be filled with a thin silicon filament. The gold is subsequently situated as small particles on the top side.
By addition of dopant atoms, the nanowires may be doped in n-conducting fashion or p-conducting fashion in its entirety or only in sections. It may also be interrupted by a dielectric region by adding e.g. oxygen or nitrogen in order to form a region of SiO2 or Si3N4 in the nanowire. A transistor structure may be produced by depositing an electrically conductive material as a thin layer on a portion of the dielectric layer provided for the nanowires. The remainder of the dielectric layer provided for the nanowires is applied thereto. After contact hole etching, an electrically conductive material that can be used as the gate electrode of a transistor is therefore situated halfway up the contact hole. For this purpose, the material has to be provided with a thin dielectric layer toward the inside of the contact hole. This may be done e.g. by oxidation of the relevant material. The nanowire is doped with different signs of the electrical conductivity, so that a channel region doped oppositely to a lower and upper source/drain region is present at the level of the gate electrode.
In the case of 3D ROMs vertical connections between two wiring planes of the chip are used for coding a memory content. If the vertical connections are formed as diodes, in which case nanowires, in particular, may be used, and the terminals of said diodes are connected at the top and bottom in each case to a bit line and word line from a columnwise arrangement of bit lines and a rowwise arrangement of word lines, ROMs can be produced in a simple manner and with minimization of the necessary area requirement.